In 1991, my employer moved to a new building. Before the move, we cleaned out storage closets containing old equipment. Much of this was obsolete gear. Things like pairs of "twiggy" disk drives removed from early Apple Lisa systems upgraded to 3 1/2" disks in 1985.
In one closet, we discovered something unusual. It was a complete Gimix III "Ghost" system. This was a 2 MHz 6809 system sporting a fifteen-slot SS-50 motherboard and eight SS-30 slots and floppy disks: a top-of-the-line 6809 system from the early 1980s.
By 1991, the company had no use for this equipment. I had the impulse to take the entire system home, but I didn't have room. My wife and I were living in a small house and the garage was already packed. She would not have been happy if I brought home a bunch of equipment.
Instead, I salvaged exactly one board -- a Gimix 256K CMOS Static RAM board. It sported 256 KB of memory, with several options, including battery backup. The rest was scrapped by an electronics recycler.
Obtaining the board, I tried it out in my system. I was able to map in 4 KB blocks of memory and test them. They all worked. I might use the additional memory as part of a virtual disk drive.
In 1994, I moved, and the entire system was stored away for over 25 years. Looking at it recently, I found it needed repair. Over the years, the backup battery failed and leaked electrolyte on the board and motherboard. Several Molex connectors are damaged, and need to be replaced. Some of the components show signs of corrosion from the battery electrolyte.
I removed the failed battery. I do hope the rest of the board still works once the repairs are complete. Perhaps I'll fix it in my retirement.
By March 1988, the MC6809E V1 card I designed in 1983 needed updates. I built an entirely new card with new features intended to run OS-9 more effectively.
CPU
A MC6809 chip simplified things with the on-chip clock oscillator. The chip handled M.RDY without extra logic, and the rising edge of the Q clock did not need delay.
Memory
The MC6809E V1 card had no on-board RAM. There wasn't room. By 1988, a number of manufacturers had 32 KB static RAMs in 28-pin packages. 64 KB of memory is realized with a couple of chips.
For the V2 board, I allowed for eight chips, totaling 256 KB of memory. This was a good compromise between cost and the space available. The memory is logically separate from the rest of the card -- decoding from the physical address and data bus, using appropriate buffers. In this way, the memory can be accessed by a bus master other than the CPU. It responds to physical addresses C0000-FDFFF or FEFFF, jumper selectable. For years, it held two chips -- 64 KB on the board -- with only 56 KB accessible. The six remaining chips were added recently, making 248 KB or 252 KB accessible.
Buffering
20-pin bus driver chips reduced the chip count, even with two sets of bus drivers, one for the CPU, and one for the memory array.
Program ROM
The design allows for a much larger ROM. The MC6809E V1 card originally had two 2KB 2716-compatible sockets -- one for a ROM and another for ROM or RAM. To make swapping OS-9 and BBUG easier, I changed this to a single 4 KB 2732-compatible ROM socket
For the MC6809 V2 board, the ROM can be a 2764, 27128 or 27256-compatible device, holding 8 KB, 16 KB or 32 KB, respectively. The larger ROM permitted more OS-9 modules to reside there, if desired.
As built, a 2764-compatible EPROM is used, containing a BBUG image in one 4 KB half, and the OS-9 ROM image in the other 4 KB half. A jumper selects which half is active. This is much easier than swapping chips to go between BBUG and OS-9.
Accessing the correct amount of the ROM requires clever decoding.
Decoder
A hard-wired decoder would limit the flexibility of the system, and it would be complex and difficult to change. Rather than discrete logic, the decoder consists of a Cypress Semiconductor CY2C291 2Kx8 EPROM. This is a fast device with a 70ns access time. The CPU address lines A5 to A15 are connected directly to A0 to A10 on the chip. The decoder is enabled with the logical OR of E and Q, which asserts during three quarters of the memory cycle. This way, the eight data output pins can be used as decoder selects programmable on every 32-byte segment of memory.
Three select lines are used: one for bus access (including the on-board memory array), one for the program ROM, and one for the DAT. Each select line is pulled up to +5v. Placing a 0 bit in the decoder ROM data array makes the select line active for that 32-byte memory segment.
Modifying the memory map becomes a simple matter of programming the decoder ROM. I programmed the following logical memory map:
0000-EFFF - Bus
F000-F77F - Program ROM
F780-F7FF - Bus
F800-FFFF - Program ROM
FFE0-FFFF - DAT (writes only)
This configuration is compatible with the existing ROMs for BBUG and OS-9, which require I/O at E000-E07F. It has 4KB of program ROM, except for the hole at F780-F7FF. This hole deserves a bit of explanation.
I/O Port Address Migration
BBUG occupies the top 2 KB of ROM. The OS-9 ROMs take up nearly 4KB. However OS9p2 doesn't use the last 128 bytes of that space. This unused space became an alternate location for the I/O ports. If the I/O ports moved from E000-E07F to F780-F7FF, the MC6809 could use RAM in the logical E block (E000-EFFF), for a total of 60 KB of RAM, up from 56 KB.
Moving the I/O address requires motherboard decoder changes and software changes to the BBUG and OS-9 ROMs, as well as revision to Flex09 and OS-9 I/O configurations. The V2 board decoder ROM would work with the existing motherboard, or with the motherboard and ROMs altered for the new I/O addresses.
Larger ROM
Once the I/O addresses are moved, the decoder can be reprogrammed to allow for more ROM space. This opens the option of moving OS-9 modules into ROM. The decoder allows the lower limit of the ROM to be changed in 32-byte increments. This allows an OS-9 system to be entirely in ROM. OS-9 would start from the reset button without requiring a boot disk.
DAT
Back side of MC6809 V2 card.
The DAT configuration is similar to the MC6809E V1 board, with one important difference. In the SWTPc MP-09 board, as well as my V1 board, the outputs of the DAT are inverted on the lower four bits (A12-A15), but non-inverted on the higher four bits (S0-S3).
This means that values programmed into the DAT must be one's complemented on the lower four bits (A12-A15), with the higher four bits (S0-S3) not complemented.
For the V2 board, all eight bits of the DAT are inverted on the bus. Thus, the value programmed into the DAT is the one's compliment of the highest eight physical address bits (A12-A15, S0-S3).
Which makes programming correct DAT values simpler, since the entire byte is complemented.
I introduced a hardware bug in the DAT decoder. More on this later.
Building
Rather than wirewrap, I opted to try something new. A technician from work gave me a couple of 3M Scotchflex Breadboarding kits. This breadboarding system was brilliant. Chip sockets connected to IDC pins. Wiring is accomplished by forcing wire-wrap wire between the IDC pins with a special tool.
It is way easier than wire-wrap, because there's no tedious cutting, stripping, threading and winding of wire. One lays the wire down and pushes it on to the pins. Wiring several connections in succession, such as with a bus, is a breeze. The results also look great. The IDC pins are low profile, so there's less chance of shorting a connection than with wire-wrap.
It's sad 3M discontinued this product. It was great. 3M has since re-used the Scotchflex brand on three other products.
Fixing the Bug
The MC6809 V2 board worked great. There were no wiring errors. I did find a problem with the DAT.
In the default BBUG and OS-9 configuration, the DAT is written once during reset and never touched. And that seemed to work just fine.
Then I started playing with an OS-9 driver called VDisk. It created a virtual disk from selected extended memory blocks. At the time, I had 56 KB of memory from the MC6809 V2 card, plus another 60 KB from the Digital Research Computers / Tanner card. That made possible a 60 KB virtual disk.
Every time I tried to access the virtual disk, the computer would crash. This took a while to track down.
I eventually realized the new decoder did not take into account the clock cycle when accessing the DAT. Transients on the R/W* line early in the clock cycle could cause bad data to be written to the DAT. After I added the missing gate, the Disk driver worked perfectly.
Usage
Like the MC6809E V1 board, this V2 board was exactly how I wanted it. There are only two jumpers.
The jumper at the top edge of the board selects the 4KB portion of the EPROM. This makes it easy to switch between OS-9 and BBUG. No more hassle of changing out chips - just move a jumper.
The jumper in the middle of the board, just above the decoder ROM enables the FE000-FEFFF block of on-board memory. This would be installed once the motherboard I/O addresses are moved out of the E-block of memory and would allow 60 KB of RAM to be used.
Future
Moving the I/O addresses out of the E-block gains 4KB more usable memory for OS-9. Perhaps I'll try that in my retirement.
Another fun project would be to put a full OS-9 Level I system into ROM. Unfortunately, all of the essential modules take up just over 16 KB of memory, so the division doesn't fall on a natural 4 KB boundary. This might cause a conflict accessing extended memory with the DAT. I'd also have to figure out how to program the decoder ROM. There are not many EPROM programmers that can program the Cypress Semiconductor CY2C291 devices, and I no longer have access to the ones I originally used.
OS-9 Level II
This design works well for OS-9 Level I. To run OS-9 Level II, which allows each process to have a full 64 KB address space, requires more hardware. First, a second set of DAT memory chips allows the user and supervisors states to have separate memory maps. Second, a means of switching between those maps automatically -- like when servicing and returning from interrupts. Third, would require ROM to be accessible from an extended memory address, and then mapped into the supervisor space.
Those requirements go beyond the scope of this design. Perhaps there's room for a V3 board. All of this assumes access to a copy of OS-9 Level II, which may be difficult to find.
To work on OS-9, I borrowed some 5 1/4" drives, and used the SWTPc DC-2 controller. This allowed me to boot up OS-9. Single-sided, single-density, 40-track diskettes hold about 100 KB -- they were quite limited on space.
Running OS-9 on single-sided, single-density 8" disks, the situation was a little better, as each drive has about 300 KB of storage. But my two-drive system was limited. Plus, I was something of an island. None of my friends using OS-9 had 8" disks, so I couldn't exchange data with them. It was time to consider 5 1/4" drives.
5 1/4" disk drives went through considerable evolution since their 1976 introduction. The early drives were single-sided, single-density with only 35 tracks. By 1987, double-sided, double-density drives sporting 80 tracks were common. These disks could hold about 640 KB, more than twice what my single-sided, single-density 8" drives held. (And more than single-sided, double-density 8" drives could as well)
Disk Controller
In August 1987, I designed a 5 1/4" floppy disk controller. The 5 1/4" controller is very similar to the 8" design, with appropriate changes for the disk interface.
A MOTOR ON* signal is generated any time the WD2797 is accessed, with a one-shot multivibrator holding that signal for 10 seconds. Another one-shot asserts the READY signal on the WD2797 after a second of MOTOR ON*. 5 1/4" disks always have the heads loaded, so HLD is tied to HLT.
Back side of 5 1/4" controller
Double-density is jumper-selectable to either follow drive select bit 7, or the SSO output. Side selection is controlled by drive select bit 6. Write pre-compensation isn't used, as it was unnecessary for 5 1/4" disks.
I built the controller the same piece of 0.1" perfboard that originally held the FD1771 disk controller for 8" disks. The board is a little bit smaller than the WD2797 controller for 8" disks, so it appears more densely packed. Wire-wrap techniques are used for the wiring, and a handful of connectors and discrete parts are soldered.
Drives
For initial troubleshooting, I borrowed the two drives and power supply from a Sage II computer from work, which I had to return. I needed my own drives.
How many drives did I need? I decided three drives would be sufficient -- one boot disk, and two working disks. This would allow me to copy disk to disk, while still having the boot disk with commands in place. (and no crazy disk-swapping for copies like the original Macintosh that had one disk drive!)
I bought two Tandon TM100-4 drives at a local hamfest. These were common surplus from Lanier word processing units at that time. When I went to buy a third drive, I could no longer find any. I ended up with a Mitsubishi M4853 drive. The specs of the drives are virtually identical, except the Mitsubishi is a half-height drive.
Drive Cabinet
5 1/4" Drive Cabinet
Finding a cabinet to house three drives was a problem. New metal cabinets are very expensive, particularly in larger sizes, and I couldn't find anything suitable on the surplus market.
September 1987, I built a wooden cabinet to proper dimensions for three TM100-4 drives. I used 1/4" plywood, reinforced at the corners with 1x1/2 strips. The bottom, back, sides and one quarter front panel are all glued together as one unit. The top screws on to the four corner posts. The finished unit is quite sturdy.
As originally built, the cabinet was plain unfinished plywood. I recently sanded and finished it with a couple of coats of polyurethane.
Inside the box, plenty of room.
Power comes from a 12 volt, 5 amp supply. 5 volts is provided from a single LM7805 regulator mounted to that supply. In retrospect, the LM7805 might be a bit over-taxed. I suspect the drives draw less power than their maximum specifications. Heat is removed from the cabinet by a small (but noisy) muffin fan on the back panel.
A power switch and neon pilot light round out the front panel, giving a clear indication the unit is on.
The controller and drives work great, easily formatting double-side, double-density disks using 80 tracks.
Drives & Software
In April of 1989, I revised all the disk drivers to handle double-density, double-sided drives. The BBUG monitor "D" command code was updated to look for double-density sectors, and the boot loader for Flex09 updated to read double-density, double-sided disks.
For OS-9, I modified an existing driver (FD2) for the Processor Technology PT69 to work with my disk controller and created a new boot disk with several drive descriptors. The drivers and descriptors allowed for 40-track disks (which required double-stepping of tracks, and adjusting the track register), and SWTPc format, where track 0 is formatted single-density -- as well as the standard, double-density, double-sided, 80-track format.
I updated the Boot module to handle double-density, double-sided disks and burned a new OS-9 ROM.
The result is a smart, efficient unit roughly the same size as the SWTPc 6800 Computer System cabinet. The fan is a little noisy, but was typical for the day.
Future
The Tandon and Mitsubishi drives only require 250 ms to get up to speed after MOTOR ON*. I can shorten the timing on the one-shot driving the READY signal.
If I can manage to find a second Mitsubishi M4853 drive, four drives would fit into the cabinet. I'd need to add a second LM7805 regulator for the 5-volt supply, and split the 5-volt output across two drives for each.
One limitation of the WD2797 is the track to track and head settling time. These drives can move track to track in 3 ms and need 15 ms for the head to settle. The WD2797, using a 1 MHz clock for 5 1/4" drives, can only do 6 ms and 30 ms, respectively.
Western Digital did manufacture another device, the WD1772-00. This was a 28-pin floppy disk controller for 5 1/4" drives that is software compatible with the WD179x and WD279x devices. The WD1772-00 allows faster track to track and head settling times -- up to 2 ms and 15 ms.
The biggest problem is finding one, as the WD1772-00 wasn't used in a lot of designs, and Western Digital stopped manufacturing them over a decade ago. Might be interesting for a V3 floppy disk controller card.
I learned about OS-9 in early 1983, when it was new. What I heard mainly concerned BASIC09 and at that time BASIC didn't interest me. That was unfortunate. OS-9 is a miniature Unix clone, optimized for the 6809.
Baud rate generator and counter/timer board
Requirements
By fall of 1986, I tired of the limitations of Flex09, and started looking at OS-9. Bringing up an OS-9 system didn't have the same challenges as Flex09, since OS-9 can format 8" diskettes. OS-9 does have additional hardware requirements. It needs a periodic source of interrupts.
Interrupt Logic
The OS-9 CLOCK module has logic for several interrupt sources, using chips available at the time. The MC6840 programmable counter/timer chip, with three 16-bit programmable counter/timers, was one option. The MC6840 fit nicely on the bit rate generator board. The driver allowed two circuit variations.
The circuit I chose exercises all three counter/timers. Timer 1 counts 50,000 cycles, then trips Timer 2 and 3. Timer 2 counts twice and signals an interrupt. Timer 3 counts down from 90. In this way, Timer 2 provides regular interrupts every 50 ms on a 2 MHz system. Timer 3 counts interrupts and adjusts the system clock whether or not the Timer 2 interrupt is serviced every 50 ms.
ROMs
The OS-9 kernel has two modules burned into ROM: OS9p1 and OS9p2. I obtained two 2KB ROMs and programmed them with the images. OS9p1 resides at F800. OS9p1 initializes the kernel, then searches for installed modules, which are position-independent. The second ROM contains OS9p2, Init and Boot. Once OS9p1 finds the OS9p2 module, it initializes it. OS9p2 looks for certain key modules, like IOMan. If they cannot be found, it uses the Boot module to load the rest of OS-9 from a floppy disk.
Once initialized, OS9p2 uses the information in the Init module to start executing. During a soft reset, OS-9 does not always load from disk. If the modules are not altered, OS9p2 can find them and bypass the boot process.
The modular structure of OS-9 allows great flexibility. Modules can be in ROM or loaded from storage devices. The Init module provides the configuration to execute the first module.
Bootstrapping
With a little help from a working OS-9 system, bootstrapping was straightforward. The ROMs I started with were pretty generic SWTPc system ROMs. The MC6840 occupied the bit rate generator board. I borrowed a 5 1/2" disk drive and plugged the DC-2 controller into I/O slot 1, with the 8" controller in I/O slot 2. Armed with a single-sided, single-density 5 1/4" boot disk, I successfully booted OS-9. That was the hard part.
From there, I created a new 5 1/4" boot disk with drivers and configuration for my 8" drives. Booting from this new disk, I formatted 8" disks and moved the OS-9 files to them. I then created an 8" OS-9 boot disk with a new I/O configuration and drivers for both 8" and 5 1/4" drives. At that point, I swapped the floppy disk controller slots, with the 8" controller in I/O slot 1, and the DC-2 in I/O slot 2. (The Boot module is configured to find a WDC-compatible floppy disk controller at the address for slot 1)
At that point, I could boot OS-9 from my 8" drives, and was able to copy files from the 5 1/4" disks. Compared with bringing up Flex09, this was easy.
I tailored my configuration to suit my hardware, and updated the ROMs with customized modules.
Swapping BBUG/Flex09 and OS-9
While I was using OS-9, I would swap back to BBUG and Flex09 on occasion. This was a pain. I would swap out the two 2 KB ROMs and use a different boot disk.
In late October of 1986, I modified the MC6809E V1 board to use a single 4 KB 2732 ROM. This put all of the OS-9 kernel on one chip, and allowed room to expand BBUG. With this modification, only one chip was swapped.
Extended Memory
Working with OS-9 uncovered an issue with extended memory addressing. December 1986, I installed a 74LS21 4-input NAND gate on the SWTPc motherboard to decode the top address bits S0-S3. This placed the I/O addresses at FE000. With the MC6809E V1 board, this worked great with BBUG and Flex09. BBUG initialized the E-block of the DAT with a value F1 -- which the board would interpret as physical address FE000.
However, I found I could not boot into OS-9 any more. Turns out, OS-9 initializes the E-block of the DAT using a value 01, which the board interpreted as physical address 0E000. With the extended addressing decoder on the motherboard, the OS-9 Boot module could not communicate to the I/O devices. This forced me to disable the 74LS21 decoder.
User Experience
OS-9 Level I uses a single 64 KB memory space for the operating system, programs and data. That's not a lot of memory. Many OS-9 programs are small, being written in assembly language. Larger programs, like a compiler, load in as multiple passes, to conserve memory use.
Using OS-9 is cool. It is a real-time, multi-tasking operating system, first available in 1982. Windows wouldn't have comparable functionality until 1989 (Windows NT), and the Mac in 1999 (MacOS X). Like Unix, you can spawn off programs to run concurrently in the background.
Using a second serial port, I ran two users simultaneously, one from the main terminal, and one from the second serial port. I used a Wyse-85 terminal on the main port, and the old CT-64 on the second port. Amazing on an 8-bit machine with 56 KB of memory!
At some point, I hung a modem on the second port. I could leave the machine running at home and dial into it from work.
By the summer of 1985, my original CT-64 terminal felt limited. Sixteen rows of 64 characters didn't seem like enough. Especially when at work I regularly used screens with at least 25 rows of 80 characters. In 1977, terminals with such capabilities were around $1000 -- way beyond my modest budget. By 1985, much more capable terminals were available for about half that price. It was time to upgrade.
August of 1985, I purchased a Wyse-85 terminal for about $700 -- a good price for the time. The terminal offed a DEC VT-220, VT-100 and VT-52 emulator, so it was plenty capable. It sported 24 or 25 rows of 80 or 132 columns on the screen. I purchased the green phosphor screen.
The most important thing, however, about the Wyse-85 compared to the CT-64 was speed. The CT-64 was limited to a paltry 1200 bps. The Wyse-85 had a top speed of 38400 bps. Thirty-two times faster. The CT-64 would take more than eight seconds to write every character on the 16 x 64 screen. The Wyse-85 could write an entire 25 x 132 screen in less than a second.
The Wyse-85 was such a joy to use compared to the CT-64, I couldn't believe I hadn't done this sooner.
I did have trouble with this terminal when I tried to use it in the shack back in the late 1980s. The keyboard scan generated a fair amount of RFI. Putting several ferrite toroids on the keyboard cable helped a little, but did not eliminate the problem.
I still have this terminal. It's been stored in the original box since November of 1994. I hope it still works.
WD2797 controller card for 8" Pertec drives in the Icom Peripherals FD360
The FD1771 disk controller works well with the Pertec 8" drives. The single-density drives each hold around 300 KB of data.
Single-density encoding is FM, which has regular clock pulses, with a data pulse placed between. A data pulse indicates a "1", a missing pulse is a "0".
Double-density uses Modified FM (MFM) encoding. It eliminates the clock pulses entirely, leaving only the data pulses. To keep synchronization during runs of zeros, extra pulses are inserted between each pair of zeros. Encoded in this way, the clock can be recovered from the data pulses alone.
Western Digital followed the FD1771 with the WD179x chips, which support double-density with a two device solution. The later WD279x chips offer the same features on a single device. Double-density allows 500 KB on the same disks, with the data transfer rate also doubled.
WD2797 8" Controller
Back side of the 8" controller
September 1986, I built a new controller using the WD2797 to support the Pertec FD400 drives. While the drives were designed for single-density, I hoped they would work using double-density.
In keeping with my other home brew cards, it's built on a piece of 0.1" perfboard with the Molex connectors epoxied to the bottom edge. Wire wrap sockets are used.
Naturally, I broke out the WWARP program I used years before to build the MC6809E V1 card.
The WD2797 design borrows from the FD1771 design. I kept the latching data bus buffer, but eliminated the redundant data bus buffers in front of them. The WD2797 performs the clock/data separation, which eliminates several gates. Fourteen total chips on this board, whereas the FD1771 board used more like eighteen.
Double-density is enabled through an option jumper. The SWTPc DC-4 controller used the SSO output to drive the DDEN* pin through an inverter. (SWTPc offered double-density before double-sided disks) One side effect of using SSO is the sector address markers will have side 0 for single-density sectors and side 1 for double density sectors.
Other designs used bit 7 of the drive select latch, controlled through software. SSO isn't connected to anything, as the Pertec drives only have one side.
A jumper at the top of the card chooses the DDEN* signal source: the SSO pin, or bit 7 of the drive select latch. Both paths go through an inverter, so double-density is selected with a 1 on either the SSO pin or bit 7.
Bit 3 of the drive select latch controls ENP - the pin for write pre-compensation. Generally, ENP would connect to the TG43 output of the floppy drive interface. Using a separate bit allows write pre-compensation to be enabled or disabled at any time, through software. I didn't know if write pre-compensation would be required or desired. It seemed like a good plan to allow write pre-compensation on any track, since the Pertec drives weren't designed for double-density.
Reading the drive select latch address returns the state of the INTRQ* and DRQ* pins, on bits 7 and 6, respectively. Using these separate bits allows more efficient loops than reading and interpreting the status bits of the WD2797. The SWTPc DC-4 introduced this feature, and is common to controllers of that era.
The WD2797 calibration starts by grounding the TEST* pin and checking three signals with a scope. A set of four pins at the base of the WD2797 chip bring these signals out making calibration easier.
To support the new controller, I re-wrote the Flex09 disk drivers to allow double-density operation.
Do the Pertec drives work at double-density? I don't know. Supporting double-density meant re-writing NEWDISK to initialize in double-density format. Before I figured that out, my interest shifted from Flex09 to OS-9, and I did not complete that project. But the card works great with single-density.
September 1985, I purchased a Kenwood TS-430S and became more active in amateur radio. In the apartment where I was living, I snuck wires out of a second floor window and began to make contacts.
In October, I got the notion to try some Radio Teletype (RTTY). I built a demodulator using a circuit I've forgotten. Perhaps it used a couple of NE567 chips. Having a demodulator, I needed to translate the five-level Baudot characters into ASCII that I could display on the terminal.
(I purchased a Wyse 85 VT-220 emulator terminal in August of 1985, so I was no longer constrained by the 64x16 screen and 1200 bps limitations of the CT-64)
RTTY Decoder
I wrote a program for Flex09 to decode 45 Baud RTTY by bit-banging a PIA pin. I couldn't use the MC6850 ACIA, because it does not support 5 bit characters.
A delay loop established character timing:
LOOP LEAX -1,X BNE LOOP
Each pass through the loop consumes 8 clock cycles. With the right value loaded in X, fairly precise timings could be accomplished. A value close to 250 would be 1 ms on a 2 MHz machine. By calling this loop repeatedly, timings of 11 and 22 ms are measured.
I connected the demodulator output to PIA Port B, pin 0. The program looks at this pin, waiting for a zero. Finding one, it calls the delay loop for 1 ms and checks again. If the pin is still zero, it waits 10 ms and checks Port B pin 0. A continued zero at this point indicates a start bit. The 11 ms total delay places us right in the middle of the start bit.
The next sequence waits 22 ms and then samples of value of Port B, pin 0. It does this five times. These samples are shifted into a byte value, which used to look up an ASCII character in one of two tables -- one for letters, and one for figures -- according to the shift mode. This character is then sent to the terminal, and we go back to waiting for a start bit.
The resulting program is about 300 bytes long. Despite the simplicity, I had little success decoding RTTY signals.
In hindsight, there are several reasons for this.
Decoding signals off the air that might have been noisy.
Demodulator circuit was completely untested and might not have worked.
No experience with RTTY, so signals might not have been properly tuned.
Precise value of the 1 ms time delay not known. I used values of 230 and 240, allowing cycles for other program logic.
At some point, I distinctly copied "RY RY RY RY RY RY RY" from someone, but not much else. Later, I figured out this meant my program, at least, was working.
Hardware Solution
In November 1986, I decided to use serial chip that could do five-level Baudot. The MC6850 only allows 7 and 8 bit characters, so I needed a different chip. The NS8250 could do 5, 6, 7 and 8 bit characters, and sports a programmable bit rate generator for all the common RTTY rates. Hence, I added an NS8250 UART to the baud-rate generator board.
Funny, though -- I never wrote software to use the NS8250. In February 1989, I removed the NS8250 and its associated circuitry.
I didn't become active in RTTY on the air until 2005, using Cocoamodem.
Some time in 1985, I had one of those moments I regretted.
I'd gotten my MC6809 system running in late 1983, running the Flex09 operating system on 8" floppy disks. I had a full set of documentation for several pieces of hardware and software. My new job kept me busy, so I didn't have much time to work with my system at home.
August of 1984, I began programming the Macintosh at work. We published our first product in March of 1985. The Macintosh was a revelation -- it completely changed the metaphor for computing. I saw early on that it was the future. But, I couldn't afford one right away. I wouldn't buy my first Mac until the summer of 1987 -- a Macintosh SE. I've only purchased Macintosh computers since that time.
In the late spring of 1985, I prepared to move to a new apartment. I had bulky boxes of documentation in my closet. I figured that I'd never do anything more with that MC6809 system -- the Macintosh was the future.
I threw nearly all of the documentation away.
Two months later, in the new apartment, I regretted my decision. There were things I could do with my MC6809 computer. I had to replace the missing documentation.
To this day, I'm not sure I found replacements for everything I had.
I graduated from Georgia Tech in the fall of 1983 and got a full-time job. By 1984, 20 KB of memory didn't seem like enough for the MC6809E V1 board. My attempt to expand the 8 KB MP-8M to 16 KB didn't work. And I never built the dynamic RAM circuits I designed. I wanted more memory.
Digital Research Computers marketed an SS-50 card designed by Tanner Computers in the early 80s. It sported thirty-two sockets for 2 KB RAM or ROM chips. These 2716-compatible chips were quite popular at the time.
I bought a kit for about $225 with a full 64 KB of RAM in June 1984.
Assembling the kit was straightforward, along the lines of the SWTPc kits. The board worked right away, with no soldering issues -- largely due to the excellent solder mask on the board.
For SS-50 systems, this board has several flexible options. The first 48 KB presents as three 16 KB banks that are enabled individually. Each 2 KB segment in the top 16 KB is enabled individually, allowing one to navigate conflicts in the C, D, E and F blocks of memory. This allowed for I/O on the motherboard, or perhaps RAM or ROM on the CPU board.
The board supports extended addressing on the S0-S3 pins. When enabled, the entire board responds as one 64 KB block. Each socket can contain either RAM or ROM chips, selectable by the jumper next to each chip.
Initially, I used this board without extended addressing as a 56 KB board. I later enabled extended addressing to access the full 64 KB, after modifying the MP-B motherboard to decode the 20-bit address for the I/O slots. This allowed me to use that 8 KB of RAM for a virtual disk drive, briefly.
I discovered some extended memory issues between BBUG/Flex09 and OS-9, so I disabled the MP-B decoding.
As pictured, the board has the E000 and E800 blocks disabled, with F000 enabled, and F800 disabled. This configuration was appropriate for the MC6809E V1 CPU board and MP-B motherboard without the 20-bit address decoding, although, technically, the E800 block could be enabled, and the F000 block would not be accessible after I modified the MC6809E V1 CPU board for a 4K ROM.
By August 1983, I had a working MC6809 computer with no storage. My BBUG monitor eschewed audio cassette tape. Floppy disk drives were expected -- BBUG included a Disk Boot command. Any disk controller needed to be compatible with that code.
In 1983, a friend of mine gave me an Icom Peripherals FD360 Dual Floppy drive box. A client of his had purchased the Icom, but opted to use another disk system instead. His client couldn't use the Icom box, but perhaps I could.
Icom was one of the first floppy disk suppliers with their "frugal floppy" system. The FD360 contained two Pertec FD400 8" disk drives, a couple of interface boards, and a large power supply. It is huge and heavy, larger than the SWTPc 6800 Computer System, and weighed about 70 lbs.
Pertec FD400
The Pertec drives differ from the popular Shugart SA800/801 of the same era. They have a 44-pin edge connector, as opposed to Shugart's 50-pin edge connector. The signals and power supply requirements are different. Icom's interface boards translated those connections into a 34-pin IDE connection, quite similar to what was later used with 5 1/4" floppy disks. There were a few important differences:
Data plate from the Icom FD360
- Step In and Step Out signals, instead of Step and Direction.
- Erase Enable in addition to Write Enable.
- 8" media data rates (250 kHz), instead of 5 1/4" data rates (128 kHz)
- Head Load signal (not present on 5 1/4" disks)
The FD400 has a single metal head, designed for single-density recording.
Western Digital FD1771
The FD1771 was the first in a series of LSI floppy disk controllers from Western Digital. It simplified the interface and operation of floppy disk drives. Designed for Shugart-style drive signals, it could accommodate the signals from the Icom with a bit of logic.
I had schematics for the SWTPc DC-2 controller, and borrowed from that design. The FC1771 data sheet convinced me that the data bus hold times meant data bus latching was required, so I had an extra layer of buffering on the data bus using a 74LS373 matched with a 74LS244 (for reads). These were on top of the pair of 74LS242s that buffered the data bus to the card.
Following the FD1771 data sheet recommendations, I used an external hardware clock/data separator. (The SWTPc DC-1,-2 and -3 all used the inadequate internal clock/data separator) I used the circuit from Figure 6 of the FD1771 application note. It has a 4 MHz clock, 74LS175, 74LS161 and a few other gates. Dividing the clock oscillator by two fed the FD1771 with 2 MHz necessary for 8" drives. A 74LS221 one-shot multivibrator supplied the head-load timing (HLT) signal after about 40 ms. A 74LS175 captures data bus D0 and D1 to a two-to-four decoder to allow drive selection -- up to four drives, but I only have two.
I built this controller using wire-wrap techniques on a piece of perfboard, with 30 pin Molex connectors glued to the edge. The same construction as I had used on the MC6809E V1 board. A 34-pin dual pin connector provided the connection to the Icom drives.
In my schematics, I included a 74LS221 one-shot to trigger the M.RDY line on the SS-50 bus when accessing the FD1771. But this pin is not available on the SS-30 bus. So I omitted the circuit during construction. The FD1771 did not need this additional delay.
The I/O slot memory map is simple:
01xx - Drive select latch (bits D0 and D1)
1000 - Command / Status Register (FD1771)
1001 - Track Register (FD1771)
1010 - Sector Register (FD1771)
1011 - Data Register (FD1771)
After building, I tested the controller by writing a few commands to the FD1771 by hand using the BBUG monitor. I could select each drive, move and load/unload the head. It seemed to work. Using the drives required a disk operating system.
Disk Operating System
At that time, 6809 systems generally ran TSC's Flex09 or Microware's OS-9. BBUG's disk boot command was designed for Flex09. OS-9 required a completely different set of ROMs. My friend Carl was already using Flex09, so that was my choice.
Upgrading from using cassette tape, a disk operating would seem like a bit step upwards. But Flex09 was very primitive, especially compared to the work I was doing with MS-DOS at the time.
Bootstrapping
SWTPc DC-2 Controller
Carl had Flex09 on 5 1/4" disks. As my disks were 8", bringing up Flex09 took some doing.
Carl gave me a SWTPc DC-2 disk controller, and loaned me his 5 1/4" drives for a couple of weeks. The DC-2 was surplus to his needs. He'd upgraded to double-sided, double-density controller, and the old controller was useless to him.
With the controller and disk drives, Flex09 booted up easily from the floppies Carl supplied. I just needed to get them on the 8" drive. The motherboard gave each controller a separate address, as they plugged into different slots. Some configuration changes let Flex09 know about the additional drives. Before anything could be copied to an 8" diskette, it had to be initialized. The 5 1/4" NEWDISK program didn't work for 8" disks as their formats were different.
I wrote my own version of NEWDISK. This required understanding the FD1771 Write Track command. NEWDISK generated all of the data for each track, with the proper address marks, gaps and codes that permitted the FD1771 to properly read and write the disk. Then it would issue a Write Track command to the FD1771 and the track data delivered. This process repeated for each track on the disk.
At the time, there was no defined format for 8" disks. Flex09 required 256 byte sectors. The 5 1/4" format used ten sectors per track in single-density. 8" disks had room for more. With very generous gap sizes, fifteen sectors per track fit easily.
After track initialization, NEWDISK would write the volume information, and then the boot loader into the first sector. A disk was made bootable simply by copying the Flex09 system files to the disk.
Experimentation
Reaching the point where I could boot Flex09 from my 8" disks, I reconfigured the system and gave 5 1/4" disks back to Carl. The work done on NEWDISK led me to experiment. With 77 tracks of fifteen sectors per track, my 8" drives held a little more than 288 KB each.
Reducing the gap sizes, seventeen sectors would fit on each track. This increased the storage capacity to 327 KB for a 77 track disk.
Doing some tests, I found that the Pertec drives were mechanically capable of 78 tracks. Trying to step out to the 79th track resulting in a very alarming klunk as the head reached its mechanical limit.
While I confirmed that diskettes formatted for 78 tracks were valid and reliable, I decided this was not recommended. Such diskettes might be unreadable on other disk drives. My final version of NEWDISK formatted 77 tracks, with either fifteen or seventeen sectors per track.
Success
By the fall of 1983, I had a working 6809 system, complete with 8" floppy disks drives running Flex09.
SWTPc 6800 front panel, sporting sixteen LEDs. Each LED indicates a 4 KB address block access. You can also see a yellow power LED was added.
The SWTPc 6800 Computer System sports a rather spartan black and silver front panel. Unlike contemporaries of its day, there were no lights.
I'd already modified the front panel of my computer. I mounted the CIS-30+ cassette interface inside the case, which accounts for the assortment of holes in the upper right. There's a yellow power LED next to the reset button. Before I went to the ISEF 1979, I replaced the power switch with a key switch. I added the yellow LED so I could tell when the machine was on.
While building the MC6809E V1 board, I decided to add some lights. Hooking up LEDs to the address bus didn't seem useful, since addresses change quickly. Plus, the DAT complicated the issue -- do you show logical or physical addresses?
I ended up with a simple solution. Running the top four CPU address lines into a 4:16 decoder, each LED indicator represents a logical 4 KB address block. This connects to the CPU board directly, before the address signals enter the DAT.
Board holding 74LS154 and LEDs.
I drilled the front panel for sixteen LEDs. On the backside of the front panel, I mounted a 74LS154 4:16 decoder and wired up the LED cathodes. The board is held in place by the LED wires. A 16-pin ribbon cable goes back to the CPU board and attaches to a socket.
This socket has address pins A12-A15 from the CPU, the VMA* signal, the DAT write decoder signal, +5 volts, and ground. The VMA* and DAT write signals go to the two Enable* pins on the 'LS154. This means the address must be valid, and not writing to the DAT to enable.
The LEDs anodes are connected together to a resistor to +5 volts. Originally, this was a 470 ohm resistor. I found that the LEDs lit very dimly. Each LED is not asserted all the time. VMA* is not asserted at all times, and pulses every clock cycle, which limits how bright the LED can illuminate. I decreased the resistor value and experimentally arrived at a value of 22 ohms.
The resulting front panel is informative. I can see when the CPU is busy-waiting on I/O ports, if it is crunching away at some calculation, or if it has crashed entirely. And if the CPU executes a CWAI instruction to wait for interrupts, all the LEDs go dark.
The bare board that held the HB 6809 V1 circuitry. Waiting for the next SS-50 project.
In computings early days, advancements happened quickly. Which mean purchases went out of date quickly. I built my SWTPc 6800 Computer System in November of 1977. In 1978, Motorola introduced the MC6809 processor, and by March 1979, SWTPc had the MP-09 CPU board available.
MC6809
For those who programmed the MC6800, the MC6809 fixed many problems. It sports 16-bit arithmetic operations, more index registers, many additional addressing modes and a very orthogonal instruction set. It was a powerhouse of an 8-bit processor. Early chips were costly, and the marketplace moved quickly beyond 8-bit chips to 16-bit ones. The MC6809 never became popular enough to dominate the market. For that brief time in the late 70s, it was the most powerful 8-bit processor. I wanted one.
Georgia Tech Symposium
In early 1983, Georgia Tech hosted a symposium where Terry Ritter, one of the designers of the MC6809 spoke. I attended, and the room was packed. Ritter talked about the design decisions that went into the architecture of the MC6809, about the importance of reusable software and position-independent code. Their design lead to the creation of BASIC09 and OS-9.
At the time, I wasn't much interested in any variety of BASIC, so I didn't pay much attention to OS-9. I should have.
The last of Ritter's talk was about an unannounced product, termed the General Motors Custom Microprocessor (GMCM). It built on the foundations of the MC6800. At that time, GM was using the MC6802 in their vehicles. The GMCM added some features to the MC6800, such as 16-bit arithmetic, an extra index register and both multiply and divide instructions. (Divide was something that the MC6809 did not have) But the GMCM lacked all the complex, orthogonal addressing modes of the MC6809. The next year, Motorola introduced the MC68HC11.
MP-09
SWTPc offered the MC6809 with the MP-09 board. The MP-09 draws from the design of the MC6800-based MP-A2 board. Both have four 2716-compatable sockets that can hold 2 KB ROM, PROM or EPROMs. While the primary difference is the CPU, there are other differences:
SS-50 bus changes for the 6809 processor
NMI and RESET switch connections relocated to a CPU board connector, which frees up two bus lines for BUSY and M.RDY, respectively
ROM socket at address F800
ROM/RAM sockets at address E000, E800, and F000
No on-board RAM. (the MP-A and MP-A2 had 128 bytes of RAM)
16 bytes of writable memory at address FFFx that translate the top 4 bits of address
This last feature is known as the Dynamic Address Translator or DAT. The DAT uses a fast 16x4 bit RAM - the 74LS189 chip. It sits between the top 4 address lines A12-A15 of the CPU and the physical bus. Thus it translates address values in 4KB blocks. It is the reason the MP-09 has no on-board RAM. The ROM monitor SBUG-E, on reset, scans addresses to determine which 4 KB blocks have RAM. It then writes the DAT to position those 4 KB blocks as desired. The first block is relocated at D000-DFFF, and the second block at C000-CFFF. These two blocks are used for the stack, and any operating system such as Flex09. The rest of the memory blocks are arranged from address 0000 upward.
The board has a socket for an additional 74LS189 chip for the DAT, which adds the four higher-order bits to the DAT RAM. This extends the address bus with four more lines (S0-S3) allowing the MC6809 to address 1 MB of memory. The S0-S3 lines take the place of the bit rate signals on the SS-50 bus, so these signals have to be supplied elsewhere for the SS-30 bus. SWTPc did this with their MP-MB motherboards, a component of the SWTPc S/09 systems.
The MP-09 board runs on the original MP-B/B2 motherboards with modifications. More on these later.
During my years in college, I eagerly wanted to upgrade my computer to the MC6809. I obtained a copy of the SBUG-E source code and studied it. By April of 1981, I modified SBUG-E, removing code for features I didn't need and adding some features of my own. I called my monitor BBUG. I used a cross-assembler on the Pr1me minicomputers to build my code. But I could not run BBUG without hardware.
MC6809E V1
My last months at Georgia Tech, I took a required course that involved building a working microprocessor system. It had to have ROM, RAM and I/O. Many of my colleagues used the computing laboratory that provided prototyping plugboards and components for their circuits.
This was a challenging course for many computer science majors. It was their first experience with digital logic. And the prototyping plugboards had been used and re-used so many times that their connections were not always reliable. This made it difficult to determine if problems were programming bugs, wiring errors, or just flakiness in the hardware.
I didn't relish dealing with flaky prototyping boards. I had fulfilled many of the requirements of this class when I built the SWTPc 6800 system in 1977! This seemed an opportunity to create my own MC6809 processor board.
I had read articles about the MP-09, and had copies of the schematics, which I studied in-depth. There were electronic parts stores and friends around Atlanta where I could obtain components. It seemed right.
MC6809 V1 Design
April 1983, I drew up schematics. My design borrowed from the MP-09, and included the DAT, but there were several differences.
I did not include an MC14411 bit rate generator or crystal. I intend to use extended physical memory right away. I moved the bit rate generator and crystal to a card plugged into the SS-30 bus. There were no bit rates on my SS-50 bus, only S0-S3 address lines.
Instead of the MC6809 chip, I opted to use the MC6809E. The MC6809 has a built-in clock oscillator and bus control logic. The MC6809E requires an external oscillator as well as a few chips to handle bus control for things like DMA. In trade, it has an LIC (Last Instruction Cycle) and AVMA (Advance VMA) pins. I made use of AVMA in my design.
Instead of four 2716-compatible 2KB sockets, I only had two. A ROM at Address F800, and ROM or RAM at address F000. Having ROM or RAM at E800 or E800 didn't make sense to me, since those addresses conflicted with the I/O ports used by SBUG-E. (In October 1986, I would revise this board to use a single 2732-compatible 4KB chip, covering F000-FFFF)
The memory map for this design was pretty straightforward:
0000-EFFF - accessing off the CPU board to the SS-50 bus
F000-F7FF - ROM/RAM socket #1
F800-FFFF reads - ROM socket #2
FFF0-FFFF writes - DAT RAM
I had no option switches or jumpers in this design. It was exactly how I wanted.
Dynamic RAM Design
The same month, I drew diagrams for dynamic RAM boards. One was a 64 KB board using 4116 chips. Another design provided 256 KB memory using 4164 chips. I intended to add one of these boards to my project. The 4116 design was complicated, with multiple voltages involved. The 4164 design was simpler, but the chips were more expensive. I never build either design.
MC6809E V1 Building
Although I had made some simple PC boards, creating one for the MC6809 design was outside my skill set. Plus, it would have been expensive for my student budget. I had constructed a seven-chip CMOS keyer in 1979 using point-to-point wiring. That was difficult. I built a duplicate keyer for my brother in 1980 using wire-wrap construction. Wire-wrap was a heck of a lot easier. Plus, I already had the tools. A friend supplied wire-wrap wire and sockets and I was in business.
Wiring a design this complex directly from the schematic worried me. Wiring mistakes were easy to make, and hard to track down. Then a classmate asked to join my project. Denise Messerschmidt worked with me in the Users Assistance office at the Computer Center, and she didn't want to have to fuss with the flaky prototype boards either. She asked if she could help, and I figured should could do the wiring of the hardware. This required good instructions.
I solved that problem with a bit of software. I used the LL(1) parser generator written by fellow student Roy Mongiovi and defined a 28 production computer "language" that described the chips and devices and the wiring between them. Given a well-described design, my program produced three lists as output.
The device list showed each device and all of the signals connected to each pin. A device was either a chip or a plug. Chips listed two pins to a line, just as it would appear on a DIP device. Plugs listed one pin to a line. The device list made it easy to verify the design was correctly programmed in the language.
A cross-reference list related the signals connected to each device. Another cross-reference list showed the signals by each device and pin. One would follow this final list to do the wiring. The Wire Wrap parser was about 2500 lines of Pascal code, and it worked beautifully.
The board used 0.1" perf-board, cut to 8 1/2" by 5" -- a little smaller than standard SWTPc boards. Molex connectors epoxied on the edge connected to the SS-50 bus. I installed the wire wrap sockets, and wired up the voltage regulator and the SS-50 pins, plus a handful of discrete components. That took care of everything that required soldering. After training Denise in wire-wrap technique, I gave her the board, wire, tools and the wiring list.
About two weeks later, she came back with the finished product. Every wire had to be manually stripped and wrapped. Denise had done an excellent job - better than I would have.
MP-B Modifications
The MP-B motherboard required modification to work with my 6809 CPU board. The I/O ports on the MP-B decode as eight, four byte ports starting at address 8000. The SBUG-E (and hence BBUG) monitor expects eight, sixteen byte ports starting at address E000.
The modifications aren't difficult:
Connect SS-50 A2 and A3 to SS-30 UD3 and UD4, respectively
Move the ABC inputs in U3 from SS-50 A2, A3 and A4 to A4, A5 and A6, respectively
Cut the trace on U3 pin 5 (Enable*) and connect to SS-50 A9
U5 has an unused NOR gate, connect the inputs to SS-50 A10 and A11, and the output to U3 pin 6 (Enable)
Move the U6 pin 4 (Enable*) from SS-50 bus A6 to A12
Move the U6 decode output on pin 4 (4*) to pin 7 (7*) this signal goes to U3 pin 3 (Enable*) and U5 pin 13 (Enable* for data bus drivers)
Modifications on underside of MP-B. The brown wires on the right go to the 74LS21.
To support extended addressing using S0-S3, the traces between the SS-50 bus to the SS30 bus for the bit rate lines 110, 150, 300, 600 and 1200 must be cut.
I added extended address decoding for the I/O ports. I mounted a 74LS21 4-input AND gate on a daughter board, and connected the inputs to S0-S3, the output goes to U6 pin 6 (Enable).
With these modifications in place, the I/O ports show up in memory as eight, sixteen byte ports, from physical address FE000 to FE1FF. The ports show up in memory four times in sequence, because address lines A7 and A8 are not decoded.
Bit Rate Generator
Bit Rate Generator Board
Since I used the extended addressing lines S0-S3 on the SS-50 bus, the bit rate signals must be provided on the SS-30 bus.
For this, I built a simple card that had just four components: MC14411, LM341-5 regulator, 1.8432 MHz crystal and a capacitor. You can see them lined up on the left side of the board. The MC14411 is the original device from the MP-A CPU board with a date code of 7718 - the 18th week of 1977.
Later, I added the MC6840 timer chip and the SN74LS04. At some point, this board also held an Intel 8250 UART, which is the reason for the molex connector in the upper right. But those parts have been removed. There's certainly room for an MC6850 ACIA or other I/O device on this board.
Bit rates are configured as follows:
110 = 38400 baud
150 = 2400 baud
300 = 300 baud
600 = 9600 baud
1200 = 1200 baud
This represents a good collection of rates across a wide range. As configured other rates are available on the MC14411 from 300 to 115200 baud.
MC6809E V1 Debugging
The beautifully wrapped board Denise wired didn't work.
When I built the SWTPc 6800 Computer System, it didn't work the first time, either. I borrowed an oscilloscope and figured out the issues. For the SWTPc 6800 boards, the problem was nearly all solder bridges. But those boards started with a working design. Mine was untested.
I had access to test equipment on campus, but I couldn't take any of it with me. I had to bring the whole computer and terminal into one of the computer center labs in the evenings, when the labs weren't in use. An oscilloscope wasn't enough. I was introduced to a new device, an HP logic analyzer -- although it took me a while to figure it out. Those evening sessions in the lab were very productive.
Dragging my computer and terminal in and out of he lab each day, I isolated six different wiring errors on the board. Had Denise let me down? No, the wiring errors were all in the original wiring listing! Denise had done her job to perfection -- she wired it exactly as specified.
Once the wiring errors were fixed, the debugging process went smoother. I also had to correct some defects in BBUG. At one point, I had all 24 channels of the HP logic analyzer engaged. 16 pins went to the address bus, and the other 8 to the data bus. This way, I could watch each memory cycle of the MC6809 and determine what was happening.
Eventually, I fixed the issues and had the system running. I received an "A" for the course. Denise, because of her limited involvement, received a "B", but we were both happy.
End of an Era
In 1988, I built another MC6809 CPU board. It replaced the V1 board, and once working, I stripped the V1 board down for parts. All that is left is a board with edge connectors and a voltage regulator, which you see at the beginning of the article.
In the early 1980s, I was excited about the MC6809 processor. I wanted one. But my student budget couldn't afford it. I studied all material about the MC6809 I could get my hands on.
In 1981, I obtained the source code to SBUG-E, the SWTPc ROM monitor for the MP-09 board. I was familiar with the source code to the MC6800 ROM monitors MIKBUG and SWTBUG. SBUG-E demonstrated the elegance of the MC6809 processor.
As I understood SBUG-E, I wasn't satisfied with it. I began to modify the source to suit my own purpose. I called this resulting monitor BBUG.
I worked on BBUG for a couple of years, off and on. My earliest printout is from April 1981. I wrote code using a cross-assembler and pour over the listings. I hunted for ways to make BBUG compact, as it had to fit in a 2 KB ROM. But the code never ran until I built the Homebrew MC6809 CPU board in mid-1983. (Which is another story)
BBUG's command structure is similar to SBUG-E, as is a lot of the code. Here are the differences.
Commands Removed
I removed several commands from SBUG-E. My plan for an MC6809 computer had floppy disks, so the cassette tape operations were the first to go. The DMAF1/2 8" disk system seemed incredibly expensive, so I removed that boot command, and used the D command character for an SS-30 floppy disk controller boot. Finally, the stack memory dump didn't seem useful to me, so I pulled it, too.
In summary:
D - no DMAF1/DMAF2 boot - no DMAFx 8" disk controller
L - no cassette tape operation
P - no cassette tape operation
S - stack memory dump didn't seem useful
U - changed this command to D, see below
Commands Added
I added a couple of new commands for BBUG. The first was a memory fill command. SWTBUG had this as well. I also added a help command.
F start-end byte - Fill Memory from start to end address with given byte value
Z - Help - prints a summary of commands
Other Changes / Refactorings
Other parts of SBUG-E were re-written and improved:
Q - I spent some time in college investigating memory test methods. I re-wrote this test to use a modulo 255 memory convergence test with nine total passes. This is a fast test that detects most kinds of memory errors.
U - Changed this command to D and completely re-wrote as an improved boot from an SS-30 Floppy Disk Controller. Major changes include:
Performs up to sixteen tries, allowing recovery from soft errors.
Alternates single and double density between tries, so it can boot from double-density disks.
Works with FD1771 and WD2797 controller chips
Works with 5 1/4" and 8" versions of controller board (more on this later)
Command code positioned in alphabetical order in source. This made no difference in the space requirements or efficiency of the monitor, but it made it much easier to find the commands I was working on.
Alter register commands refactored to use less space.
The last iteration of BBUG v1.91 fits in a 2 KB EPROM with 1 byte to spare.
4 KB Version
In October 1986, I experimented with expanding BBUG to fit a 4 KB ROM. This version has a test string at address F000, and the rest of BBUG at address F800. You can see this version at the bottom left in the picture above.
The test was successful, and this left space for more commands. At that point, however, I was more interested in OS-9, and had less use for BBUG.
Future Changes
If I make any future modifications to BBUG, the first thing I'd do is a fix a bug. The extended memory initialization assumes that the E-block is at physical address FE000, so it writes F1 into that block. That's not compatible with the current Homebrew MC6809 V2 board (which is another story), where the value should be 01 instead. This would also match the value written by OS-9 Level 1.
There's also 2 KB of additional space for more commands. Extended memory functions would be welcome. A command to catalog all the extended memory blocks would be useful, as well as running memory tests on extended memory blocks. That would be a start. And I might bring back the stack memory dump command.
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